Implementing the CRC algorithm in hardware

The hardware CRC implementation is shown in the next figure. The Implementation shown is for a specific set of parameters:

Message M=1010001101
Pattern P=110101
FCS F=1110 (to be calculated)

The circuit is implemented as follows:

1. The register contains n bits, equal to the length of the FCS
2. There are up to n XOR gates
3. The presence or absence of a gate corresponds to the presence or absence of a term in the divisor polynomial P(X)

The same circuit is used for both creation and check of the CRC. When creating the FCS, the circuit accepts the bits of the raw frame and then a sequence of zeros. The length of the sequence is the same as the length of the FCS. The contents of the shift register will be the FCS to append. When checking the FCS, the circuit accepts the bits of the received frame (raw frame appended by FCS and perhaps corrupted by errors). The contents of the shift register should be zero or else there are errors.